| PART |
Description |
Maker |
| UPD42S16100LLA-A80 UPD42S16100LG3-A80-7JD UPD42S17 |
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
9-Mbit (256K x 32) Pipelined DCD Sync SRAM
9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
x1 Fast Page Mode DRAM x1快速页面模式的DRAM
|
TOKO, Inc.
EPCOS AG
|
| CY7C1355C-117BGC CY7C1355C-117BGI CY7C1355C-117BZC |
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture 256K X 36 ZBT SRAM, 7.5 ns, PBGA165
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture 9兆位56 × 36/512K × 18）流体系结构，通过与总线延迟静态存储器
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| CY14B104L-BA15XCT CY14B104L-BA15XI |
4 Mbit (512K x 8/256K x 16) nvSRAM 512K X 8 NON-VOLATILE SRAM, 15 ns, PBGA48
|
Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
| CY7C1354DV25-200BZI |
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture 256K X 36 ZBT SRAM, 3.2 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY14B104L-BA15XI CY14B104L-BA15XIT CY14B104L-BA25X |
4-Mbit (512K x 8/256K x 16) nvSRAM
|
Cypress Semiconductor
http://
|
| CY14B104LA-ZS20XI CY14B104LA-BA45XC CY14B104NA-BA4 |
4 Mbit (512K x 8/256K x 16) nvSRAM
|
http://
Cypress Semiconductor
|
| CY7C1363C-133AXC |
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM 512K X 18 CACHE SRAM, 6.5 ns, PQFP100
|
Cypress Semiconductor, Corp.
|
| CY7C1361B CY7C1361B-100AC CY7C1361B-100AI CY7C1361 |
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
|
CYPRESS[Cypress Semiconductor]
|
| CY7C1363C-100AJXC CY7C1363C-100AJXI CY7C1363C-100A |
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
|
Cypress Semiconductor
|
| CY7C1461AV33-100AXC CY7C1463AV33-100AXC CY7C1461AV |
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL垄芒 Architecture
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL Architecture(带NoBL结构6-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM) 36兆位米x 36 / 2 M中的x 18/512K × 72）流体系结构，通过与总线延迟（带总线延迟结构的的36 - Mbit通过的SRAM100万x 36 / 2 M中的x 18/512K × 72）流的SRAM
|
Cypress Semiconductor Corp.
|
